Diagram showing the SimTEC architecture in glass substrate with SimTEC vias operating in the central region of the electronic chips (EIC) and photonic chip (PIC) with the chip’s peripheral I/Os dedicated for electrical connection in the photonic package (IMAGE)

SPIE--International Society for Optics and Photonics

Diagram showing the SimTEC architecture in glass substrate with SimTEC vias operating in the central region of the electronic chips (EIC) and photonic chip (PIC) with the chip’s peripheral I/Os dedicated for electrical connection in the photonic package

Caption

Diagram showing the SimTEC architecture in glass substrate with SimTEC vias operating in the central region of the electronic chips (EIC) and photonic chip (PIC) with the chip’s peripheral I/Os dedicated for electrical connection in the photonic package. 

Credit

The Authors, doi: 10.1117/1.JOM.4.1.011006.

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