Solving the trilemma (“polarizability”- “scalability”-“insulation robustness”) in down-scaling a gate layer of a transistor. (IMAGE)
Caption
Using a superparaelectric high k dielectric to solve the trilemma in a gate layer (“polarizability”–“scalability”–“insulation robustness”). (a) “low (k) and scalable” simple oxide gate layers facing the challenge of electrical breakdown with a physical thickness approaching the quantum tunneling limit; (b) “high (k) and non-scalable” complex polar oxide gate layers facing the same challenge as in (b), with a higher threshold of the smallest physical thickness due to a lower breakdown strength (Ebd); (c) “high (k) and scalable” SPE gate layers having both a thickness-scalable high k and a large Ebd.
Credit
Journal of Advanced Ceramics, Tsinghua University Press
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License
CC BY