Block diagram of the proposed full-duplex (FD) transceiver (IMAGE)

Tokyo Institute of Technology

Block diagram of the proposed full-duplex (FD) transceiver

Caption

The proposed architecture focuses on minimizing self-interference (SI), the leakage of the transmitted signal (TX) into the receiver (RX). By adopting a symmetric antenna design and implementing a more precise self-interference cancellation (SIC) circuit, the system can reach unprecedented data rates at frequencies over 100 GHz.

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©2023 VLSI Symposium

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