KAIST Solves 3D Memory Reliability Problem with "Oxygen Tunnel" Structure, Boosting AI Chip Performance and Reducing Power Consumption (IMAGE)
Caption
Figure 3. Oxygen-Tunnel Vertical Channel Transistor eDRAM Benchmark Framework and System-Level Performance Evaluation
Based on device characteristics obtained through experiments, the team built a TCAD model and converted it into a compact model to evaluate performance at the circuit and compute-in-memory (CIM) level. The hybrid eDRAM structure combines the oxide vertical channel transistor with silicon CMOS: the oxide vertical channel transistor was designed to provide long data retention through its low leakage current, while silicon CMOS was designed to handle fast read speed and high reliability. Comparing the 3D integrated structure and layout of the proposed hybrid eDRAM, stacking the oxide vertical channel transistor on top of silicon CMOS reduced cell area by about 38% compared to the conventional structure, enabling higher memory density. In addition, comparing the storage-node voltage over time showed a characteristic improvement of about 45-fold over conventional silicon-based eDRAM.
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KAIST
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