Improving chip design on every level

A programming framework could streamline chip design by bridging the gap between conceptual design and practical execution^[1]. This may help address the ongoing challenge in the computer hardware industry of meeting the demand for high-performance, energy-efficient electronic devices at ever smaller scales.

This demand has long posed a challenge: it requires not only smaller transistors and microchips but also innovative new hardware architectures that provide the optimum arrangements of components for rapid data flow and processing. However, transforming a high-level design — exactly what we want a chip to do — into the low-level details of practical hardware is a lengthy, complex process requiring multiple iterations and collaboration across multiple teams.

In developing the framework, called Assassyn (ASynchronous Semantics for Architectural Simulation and SYNthesis), researchers—including Jian Weng from KAUST—incorporated both architectural simulation and real-world hardware implementation.

Digital computer systems contain interconnected information-storing modules called registers. Register-transfer-level (RTL) languages like Verilog represent the circuit connections between registers, while the designers focus on the overall behaviors of the circuit. This imposes a gap between the design process and the real implementation (the actual wiring of a chip).

“Most chip design research adopts two separate styles: performance is simulated, while power-per-area characteristics are estimated through a separate RTL implementation,” says Weng. “This means there is a mindset misalignment between design and implementation. When designing, you think about doing jobs at one stage and ‘pushing’ data to the next. When implementing in RTL, you need to translate it into a ‘pull’ style in your mind — the latter stage listens for the signal to pull data in.”

Most efficient chip designs include ‘pipelining’ architectures, which allow multiple tasks to be executed simultaneously, keeping many transistors active and saving time — analogous to a factory assembly line. A key challenge in pipeline implementation is the coordination between stages.

“Our insight is that the behavior of pipeline stages cannot take effect immediately,” says Weng. He and his co-workers found that the secret to unifying the design and implementation stages was that events do not all have to happen at the same time.

“In Assassyn we use asynchronous event handling, a widely adopted programming paradigm in website development,” says Weng. “When functions are called, they are not executed all at once. This asynchronicity is the key innovation that makes Assassyn work.”

The team’s evaluation showed that Assassyn generated accurate, high-performance RTL simulations, achieving an order of magnitude speedup over previous models. To avoid reinventing the wheel, Assassyn-generated RTL can directly fit into existing design tools. The results showed that the generated RTL matched the quality of laboriously handcrafted designs in terms of power, chip area, and performance.

“Many hardware design concepts have already converged to their optimal points over the past few decades,” says Weng. “Instead of manually programming every detail of the hardware implementation, some common behaviors can be abstracted in a high-level manner.”

“We are now actively working in several directions, including building new hardware using Assassyn, building better ecosystem support for Assassyn, and extending the abstraction of Assassyn for the next best hardware design and implementation,” concludes Weng.

Reference

1. Weng, J., Han, B., Gao, D., Gao, R., Zhang, W., Zhong, A., Xu, C., Xin, J., Luo, Y., Wills, L.W. & Canini, M. Assassyn: A unified abstraction for architectural simulation and implementation. ISCA ’25: Proceedings of the 52nd Annual International Symposium on Computer Architecture, 1464 – 1479 (2025).| article