Hanyang University researchers propose 108 Gb/s PAM-8 receiver frontend system in 28nm CMOS
The novel technology is expected to revolutionize data centers, AI clusters, the metaverse, networking equipment, and supercomputers
image: The proposed multi-path architecture leads to a remarkable data rate of 108 Gb/s with total power of 210.8 mW.
Credit: Sangwan Lee from Hanyang University
High-voltage, higher-order PAM-8 signals are essential to achieve data rates beyond 100 Gb/s, requiring highly linear receivers to maintain excellent signal-to-noise ratios.
In a recent breakthrough work, a team of researchers, led by Mr. Sangwan Lee, an integrated M.S. and Ph.D. degree student in electronic engineering, and Dr. Jaeduk Han, an Associate Professor of electronic engineering, at Hanyang University, South Korea, has proposed a multi-path architecture with enhanced linearity-power trade-off. The novel highly linear receiver frontend system with two-tap feed-forward equalizer (FFE) capability in 28nm CMOS exhibits a remarkable data rate of 108 Gb/s and an input range of 1.4 Vppd with 210.8 mW total power and 1.95 pJ/bit efficiency.
This next-generation technology was presented on November 4 at the IEEE Asian Solid-State Circuits Conference (A-SSCC), one of Asia’s premier semiconductor conferences.
Mr. Lee remarks: “In this research, we have maximized both power efficiency and signal processing capability through two unique architectures for processing 'PAM-8' signals, which are essential for next-generation high-speed communication.”
The researchers first dramatically improved the linearity-power trade-off through a 'multi-path architecture.' They designed the architecture by dividing the signal path, allowing each path to handle a sub-range of the total dynamic range. As a result, the number of required slicers or samplers was reduced, decreasing the load on the final stage and facilitating the achievement of remarkable efficiency: doubling the linearity with only 20% power increase.
Next, the team effectively compensated for channel loss through a 'separated FFE path.' Since high-speed signals suffer significant channel loss, compensation via an FFE is essential. However, in conventional receiver architectures, the FFE must directly process large-voltage signals, leading to signal compression. The researchers designed a structure that completely separates the FFE path from the main path, allowing it to calculate the compensation value using only a small, attenuated signal. This approach fundamentally prevents compression, enabling successful channel loss compensation even while handling large input signals.
This technology is poised for immediate application as a core component in next-generation high-speed data communication infrastructure. Its key application areas include data centers and Artificial intelligence (AI) clusters, wherein dramatically increasing the communication speed between servers can significantly facilitate the training of large-scale AI models and the processing of massive datasets, as well as next-generation networking equipment that forms the foundational technology for future 800G and 1.6T Ethernet systems.
Furthermore, the present research could help accelerate the computational speed of supercomputers used in advanced scientific research and simulations.
In the next 5 to 10 years, this work will serve as the foundational technology that accelerates the development of next-generation applications, including more powerful and widespread AI, metaverse and AR/VR era, and sustainable data centers. “It will provide the backbone for complex AI services like real-time translation, advanced medical diagnostics, and autonomous driving systems to become faster and more universally available. Moreover, by providing the massive bandwidth required for immersive virtual and augmented reality experiences, it will help make a seamless virtual world a reality. Lastly, as global data demand continues to explode, our power-efficient approach will help reduce the energy footprint of data centers, contributing to sustainable technological growth,” concludes Dr. Han.
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Reference
Conference: IEEE ASSCC 2025
About Hanyang University
Hanyang University traces its roots back to 1939 when the Dong-A Engineering Institute was established. By 1948, the instate had transformed into the nation’s first private university, evolving into Hanyang University in 1959. At its core, Hanyang University upholds the Founding Philosophy of “Love in Deed and Truth,” and its mission is to provide practical education and professional training to future experts and leaders. With a rich history spanning nearly a century, Hanyang University continues to uphold its core values while adapting to the evolving landscape of education and research, both domestically and internationally.
Website: https://www.hanyang.ac.kr/web/eng
About the authors
Mr. Sangwan Lee received his B.S. in Electronics Engineering from Inha University, Incheon, South Korea, in 2021. He is currently pursuing an integrated M.S.–Ph.D. in Electronic Engineering at Hanyang University, Seoul. His research focuses on high-speed wireline communication and automated design of high-performance integrated circuits.
Dr. Jaeduk Han received his B.S. and M.S. in Electrical Engineering from Seoul National University, Seoul, South Korea, in 2007 and 2009, and his Ph.D. in Electrical Engineering and Computer Sciences from the University of California, Berkeley, USA, in 2017. He is an Associate Professor of Electronic Engineering at Hanyang University, Seoul. His professional experience includes positions at TLI (South Korea), Altera, Intel, Xilinx, and Apple (USA), where he worked on digital, analog, and mixed-signal IC design and automation. His research interests include high-speed analog and mixed-signal circuit design and design automation.