A printed liquid-metal fix bypasses the atomic limits of 2D microchips

A printed and defect-rich oxide layer can significantly reduce the electrical barriers in next-generation microchips, according to a study that tested liquid-metal contacts on two-dimensional semiconductors.

In the International Journal of Extreme Manufacturing, a study found that transistors built with this technique achieved high electron mobility and ultra-low resistance, bypassing the strict physical limitations that have historically stalled the scalable industrial production of 2D electronics. The approach also hints that deliberate structural imperfections can be engineered to solve interface bottlenecks without damaging fragile device components.

A manufacturing bottleneck

Two-dimensional materials like tungsten disulfide offer a pathway to faster and smaller electronics. However, injecting electricity from traditional metal wires into these atomically thin sheets creates a massive electrical roadblock known as contact resistance.

Engineers often try to fix this by inserting an insulating tunneling layer, like hexagonal boron nitride, to smooth the transition. But this approach requires layers exactly 0.5 nanometers thick - a tolerance that is virtually impossible to maintain reliably across a commercial assembly line.

To bypass this constraint, Yun Li and his coworkers from Wuhan University of Technology and Songshan Lake Laboratory turned to liquid gallium. By printing the liquid metal across a surface at room temperature, they deposited a uniform layer of gallium oxide just 3.6 nanometers thick. This low-temperature process is gentle enough to avoid damaging the underlying 2D materials, sidestepping the destructive heat and chemical bonding of traditional deposition methods.

Stepping stones for electrons

The printing process naturally leaves the gallium oxide starved of oxygen, meaning 67% of the expected oxygen atoms are missing from the structure initially. Rather than acting as a flaw, these oxygen vacancies form energetic stepping stones within the material.

Instead of forcing electrons to vault across a high energetic wall in a single leap, a challenging physical process known as direct tunneling, the electrons hop sequentially from one oxygen vacancy to the next. This mechanism, known as defect-assisted tunneling, effectively shrinks the contact barrier height to just 3.7 millielectron volts.

The resulting differences in transistor performance were stark. Devices built with the printed tunneling layer hit a peak electron mobility of 296 cm²·V^-1·s^-1). More importantly for factory-floor integration, the contact resistance dropped to 2.38 kΩ·μm, which is roughly two orders of magnitude lower than what is achieved with conventional tunneling contacts.

While the team successfully fabricated a functional array of transistors on a 1.5-centimeter silicon chip, the work currently relies on manually exfoliated flakes of 2D material, which inherently causes performance variations. The required next step for industrial deployment is to map the exact energy distribution of the oxygen defects and combine the printing technique with large-area and chemically grown 2D films to achieve uniform wafer-scale integration.

DOI: 10.1088/2631-7990/ae51d2

International Journal of Extreme Manufacturing (IJEM, IF: 21.3) is dedicated to publishing the best research related to the science and technology of manufacturing functional devices and systems with extreme dimensions (extremely large or small) and/or extreme functionalities

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